1. Field of Invention
The field of the present invention relates in general to methods and apparatus for digital-to-analog conversion and more particularly to a non-uniform sampling rates for digital-to-analog conversion.
2. Description of the Related Art
There are two standard methods for increasing the signal to quantization noise ratio (SQNR) of a digital-to-analog converter (DAC). First, one can increase the bit precision of the DAC. While this is conceptually the most straightforward technique, this complicates the analog circuit design. For large bit precisions, analog non-linearities will dominate performance. Removing these non-linearities, if possible, requires complicated design and calibration procedures. A second standard method for increasing DAC performance is to interpolate the digital signal to a higher sample rate using well-known signal processing techniques, such as those described in xe2x80x9cMultirate Digital Signal Processingxe2x80x9d by R. Crochiere and L. Rabiner, published by Prentice Hall Inc. 1983 which reference is incorporated herein by reference. Interpolation spreads some of the quantization noise out-of-band relative to the input signal, where it can be removed by a filtering operation at the receiver. The drawback to this second method that the DAC must run at a higher clock rate, thereby requiring more power.
What is needed are ways to improve DAC performance while minimizing analog complexity or minimizing power consumption.
An apparatus and method is disclosed for a digital-to-analog converter (DAC) system with both uniform and non-uniform sampling rates. The system includes a digital portion in which samples of a set of xe2x80x9cNxe2x80x9d digital samples are obtained from a digital input stream Each set of samples is evaluated with various test decimations which may include various combinations of uniform and non-uniform timing intervals between the selected members of each decimation. Each test decimation includes substantially the same number xe2x80x9cMxe2x80x9d of digital samples where xe2x80x9cMxe2x80x9d is less than the number of samples xe2x80x9cNxe2x80x9d in each sample set. Each test decimation is digitally evaluated to determine which is the optimum test decimation. The optimum test decimation exhibits the best fit with the original set of xe2x80x9cNxe2x80x9d samples using a reduced set of xe2x80x9cMxe2x80x9d digital samples. This optimum test decimation along with the appropriate timing information is subject to an digital-to-analog conversion, with the corresponding analog output signal retaining a high degree of fidelity with the digital input signal albeit at a reduced average sampling rate. The reduction in sampling rate for the DAC simplifies circuit design and reduces power requirements.
In an embodiment of the invention an digital-to-analog converter (DAC) system for converting a digital signal to a converted analog signal is disclosed. The DAC system includes a DAC and a variable decimator. The DAC includes a digital input, an analog output and a sampling input. The sampling input is responsive to a sampling signal to control sampling intervals for digital samples at the digital input. The variable decimator effects for each successive set of N digital samples an optimum decimation thereof into M corresponding digital samples with M less than N and with at least one optimum decimation including non-uniform time intervals between selected samples thereof The variable decimator further delivers at least the corresponding M digital samples of each optimum decimation to the digital input of the DAC together with a sampling signal. The sampling signal includes timing information for the M digital samples within the corresponding set of N digital samples.
In an alternate embodiment of the invention a method for a DAC is disclosed which comprises:
sampling the digital signal to obtain a first set of N digital samples thereof,
generating a plurality of test decimations of the first set with each of the plurality of test decimations including M digital samples with M less than N and with selected ones of the plurality of test decimations exhibiting varying timing intervals between the corresponding M digital samples;
selecting an optimal one of the plurality of test decimations;
converting the optimal one of the plurality of test decimations to an analog signal with timing thereof corresponding with timing information for the M digital samples of the optimal one of the plurality of test decimations within the first set of N digital samples; and
repeating the sampling, generating selecting and converting acts for successive sets of N digital samples.